Tools and Systemsupport for a New Scalable Dsp Architecture

The ongoing advances in semiconductor technology are the enabler for complete System on Chip (SoC) solutions. In this SoC domain Digital Signal Processors (DSPs) are employed to carry out software driven digital signal processing tasks. Although DSPs could still be modified in the SoC domain, they are mainly employed as fixed DSP cores. Possible adaptations to the embedding system cannot be carried out. Thus, our work is targeted to design expandable DSP architectures. To achieve this expandability, we designed a sliced DSP architecture. Here, the number of slices can be adapted towards system needs. Specific system requirements can be achieved by adding dedicated datapaths to these slices. With this approach one magnitude of order in performance boost can be achieved, which creates new demands for I/O processing. Thus, within our DSP architecture we integrated a dedicated I/O processor. In this paper we present this new scalable DSP architecture, tools to map algorithms which include onto this DSP architecture, and the concept of our new I/O controller. These methods are developed and currently refined in more detail in close conjunction with SFB 358 project A1 (loop transformations) and SFB 358 project G, including system requirement (G1 and G3) and operating system issues (G2). The resulting technologies allow to easily adapt our DSP architecture to different system requirements.